core_ddr3_controller
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ultraembedded
A DDR3 memory controller in Verilog for various FPGAs
Hi, I would like to ask how I could use your core with Microblaze in block design? Thank you for your help!
Hello, I got the ECPIX-5 example working at 50 MHz, it seems great. I'm getting about 50 MB/s if I read in a loop using the `ddr3_core` interface. However, I'm...
As the title implies, this PR adds a Makefile flow to quickly create the Makefile project and generate bitstream for available targets. Currently, the support for ARTY-A7 is added and...
This avoids "used before declaration" errors from Vivado. Issue: #6
Compile error resulting from compilation in Vivado 2023.2. ``` ERROR: [VRFC 10-3380] identifier 'awvalid_w' is used before its declaration [/home/filmil/.cache/bazel/_bazel_filmil/fba57cb1498e5edac648620d88e186c0/external/core_ddr3_controller/src_v/ddr3_axi_pmem.v:173] ``` Inspecting the source code, this seems to be a...
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A DDR3 memory controller in Verilog for various FPGAs