ECPIX-5 maximum speed

[petersn]

Hello,

I got the ECPIX-5 example working at 50 MHz, it seems great. I'm getting about 50 MB/s if I read in a loop using the ddr3_core interface. However, I'm curious about speeding this up to like 100 MHz. The default settings of:

ecp5pll
#(
   .in_hz(100_000_000)
  ,.out0_hz(50_000_000) // clk_w
  ,.out1_hz(50_000_000) // clk_ddr_w, 90 degree phase shift
  ,.out1_deg(90)
) ...;
ddr3_core
#(
  .DDR_MHZ(50),
  .DDR_WRITE_LATENCY(3),
  .DDR_READ_LATENCY(3),
) ...;

work great. However, I if I do:

ecp5pll
#(
   .in_hz(100_000_000)
  ,.out0_hz(100_000_000) // clk_w
  ,.out1_hz(100_000_000) // clk_ddr_w, 90 degree phase shift
  ,.out1_deg(90)
) ...;
ddr3_core
#(
  .DDR_MHZ(100),
  .DDR_WRITE_LATENCY(3),
  .DDR_READ_LATENCY(3),
) ...;

then the bottom 16 bits I read are always wrong. If I adjust the latency values down (to 2 and 2) then I read zeros, and if I adjust them upwards I get other errors, like totally wrong values. (I should mention, yosys+nextpnr say everything should pass at 140 MHz, so I don't think there are any timing closure issues.)

Any suggestions here? I'm also a tad scared about how sensitive this seems to be to these parameters. I'm not sure how to tune them more generally, for my own custom boards with an ECP5 device and a DDR3 SDRAM chip.

Thanks,

-Peter