Automated Makefile flow for FPGA project creation and bitstream generation

[aitesam961]

As the title implies, this PR adds a Makefile flow to quickly create the Makefile project and generate bitstream for available targets. Currently, the support for ARTY-A7 is added and tested. However, the flow supports flexibility of easily adding more boards from Xilinx and Lattice into the system.

This PR is in the direction of a wider effort to automate the building process of an SoC based on Ultraembedded components including RISCV-SoC, DDR MC, DVI-Framebuffer and Bi-RISCV.

Queries and suggestions are welcome.