Genadi V. Zawidowski

Only two lines.,.. Same problem and similar for aarch64 processors `From 909ee3f39a3c5f6cc2d99fcab48ae6fc4e09371a Mon Sep 17 00:00:00 2001 From: ua1arn Date: Wed, 15 Mar 2023 18:09:59 +0300 Subject: [PATCH] risc-v compatibility...

Error: invalid literal constant: pool needs to be closer

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This error message from linker stage of gcc point to this line of code:  Ths fuction - inline body of **__FPU_Enable**, located in `core_A/Include/cmsis_gcc.h`. In my project with -Ofast...

Propose add CPUECTLR access functions.

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How about adding this functions to _CMSIS/Core_A/Include/cmsis_cp15.h_ ? This register used for support SMP data coherency in conjunction with ACTLR. ``` #if (__CORTEX_A == 8U) #define CPUECTLR_SMPEN_Msk (1u

GIC_SetConfiguration safety

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I propouse add stripping extra bits in argument. Existing implementation fails then used unstripped value from GIC_GetConfiguration 

Cortex-A build fix

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 Case mismatch.

Core-A: modifications for representation interrupt mode model on Rene…

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Core-A: modifications for representation interrupt mode model on Renesas Cortex-A9 RZA1x CPUs

aarch64 stubs

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I am use these modified files for hide warnings while aarch64 compilation: Propose add as seed of adding aarch64 (coretex-a53) support. [Include.zip](https://github.com/ARM-software/CMSIS_5/files/9593540/Include.zip)