tpagarani

Results 6 comments of tpagarani

@rakeshm75 could you please validate this change through complete openfpga flow to make sure that it passes.

@mkurc-ant could someone review this PR and merge?

@rakeshm75 please help review the changes

@mkurc-ant can we put the expansion of BRAM macros under a new flag in synth_quicklogic.cc and turn if off by default. We would like to control this feature with a...

@mkurc-ant Can you merge this PR after putting the code under a flag as I requested

@mithro, well the reason I mention VPR is that sdf writer is part of VPR. Timing graph already has timing arcs and setup/hold, it's just that it's not being written...