RISC-V topic
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
eide
An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
shecc
A self-hosting and educational C optimizing compiler
Maxine-VM
Maxine VM: A meta-circular research VM
rars
RARS -- RISC-V Assembler and Runtime Simulator
jupiter
RISC-V Assembler and Runtime Simulator
rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.
RISCV-Simulator
đŸ’» RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.