electronic-design-automation topic
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Parser-Verilog
A Standalone Structural Verilog Parser
rl4co
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
naja-verilog
A standalone structural (gate-level) verilog parser