HDL-deflate
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FPGA implementation of deflate (de)compress RFC 1950/1951
Starting from reset, I send the following input block in static mode, 0x18 0x19 0x72 0x04 0x00 (which is compression of 'A'), then set imode == DECOMPRESS in next cycle...
In my current design, input data width is 256bit. In deflate.v, the input i_data & output o_byte are 8bit. How can I extend the data bus to 256bit?
Hi, I set up deflate.py with a 32768 OBSIZE and COMPRESS = False. I wrote C code based on test_deflate.py. When it runs, the first 5 bytes that are output...
Hello, This looks like a very interesting project. But, since I have never used MYHDL could you please describe how to get started with for example the Vivado project? I...
Hi, I found that python zlib compression efficiency is better than this hdl project in your test file. Is the main reason matching length different between python zlib and hdl...