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FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardwa...

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I try to synthesize the following example from Haskell to Verilog ``` { mAdd isZ g m1 m2 = case m1 of { QError -> QError ; QNone -> m2...

# Environment * Ubuntu 20.04.02 * GNU Make 4.2.1 * Icarus Verilog version 10.3 (stable) () * Glasgow Haskell Compiler, Version 8.6.5, stage 2 booted by GHC version 8.6.5 *...

The yosys suite supports the ECP5 family of FPGAs, would the Reduceron work with such a combination? A quick glance at the Cyclone IV says the max gate count is...

Hello, I've been trying to run the examples in Flite, but some of them are giving unexpected results. For instance, the Fibonacci one gives the following output: ``` C:\Users\VitorCBSB\Reduceron\flite>stack exec...

This is a generalization of issue #14. The Recipe semantics is not ideal, in particular variable assignments do not take effect in the same cycle. This makes for Verilog semantics...

York Lava uses unsafePerformIO to implement Observable Sharing, but unsurprisingly this is extremely fragile. It currently can break down when experimenting in the interpreter, leading to bizarrely malfunctioning RTL from...

When writing code for Reduceron, I currently start with Haskell program and manually translate it to Flite, including adding whichever library/prelude functions I use. This is pretty tedious. Unfortunately, hf...

The Altera and Xilinx mappers do a much better job with stylistic HDL. It wouldn't be hard to expose muxes are a few other idoms. It's TBD whether generating busses...

This is the Lava dual of the emulator bug fixed in aadd78cf where the sharedness can be lost in copyChild. What happens is that we see an already copied app...