Port to yosys and ECP5?

[shapr]

The yosys suite supports the ECP5 family of FPGAs, would the Reduceron work with such a combination?

A quick glance at the Cyclone IV says the max gate count is about 150,000. The ECP5 gets as large as 85,000 gates, that's a big difference.

Any idea how many gates are used with the current design?

[tommythorn]

I just noticed your issue, apparently I wasn't getting notifications :(

Yeah, I really should get on with a port (or even better, help someone else with one). As for your question, Reduceron doesn't actually take that many LUTs/FFs (I forgot the count), but the biggest issue is that currently the heap is completely implemented with blockrams (uses no external memory), thus there's a minimum needed to run all examples and there's a number below which performance degrades exponentially do with GC running more and more frequently.

I don't recall the precise numbers, but the rule of thumb I was using was that 4.6 Mb was near the minimum I'd consider. The largest ECP5, the 85F has only 3.7Mb (not including 0.6 Mb of distributed memory) so it's probably to small to run all the examples [fast], but certainly can run some of them.

I actually did take a quick stab at it many months ago but ran into Yosys not being able to infer true dual-ported rams. It's not the end of the world (just instantiate the blocks), but it was more work than I was willing to do at the time.

The way to proceed is almost entirely about adding support for ECP5 to Red-Lava; and that is almost all about adding support for the ram blocks, so it's not too bad. Once all the examples run, Reduceron should run as well.

This would happen sooner if a volunteer came forth to drive this.

[tommythorn]

This is one of the issues I referred to: https://github.com/YosysHQ/yosys/issues/1101