thunder-hammer

Add some additional information to the documentation

2

Clarify the difference between children and references in the definition We have the instance object defined but it may be confusing what children and references are in the context of...

Additional visualization example file

6

Thanks to JensRestemeier and Jordi1215 we have some example scripts that show how to create a netlist from the ground up in SpyDrNet. Now that we can create it would...

Documentation improvements and clarifications

1

A user of the documentation suggested the following improvements * The documentation is too FPGA specific and it should be expanded out to include asic designer and others * It...

Create a built in construct and move module/cell parameters out of the metadata

1

It would be nice to add the parameters into the intermediate representation direction. Currently to do a cross language conversion from EDIF to Verilog or vice versa requires the composer...

Verilog Parser features required to parse Quartus Prime .vo/vqm files

4

Currently I only have one example of each of these formats. There could be a lot more constructs than what I see. VO files ---------- defparam structure `defparam \avs_s1_readdata[12]~output .bus_hold...

Clean up the namespace managers' implementations

2

Currently the namespace managers are somewhat confusingly implemented. * They use static methods that are difficult to override but the EdifNamespace and DefaultNamespace share most of the same code. *...

It would be useful to make sure the handling of constant assignments and port mappings makes sense, and compare with what we are doing with the EDIF parser/composer. some example...

Some things we noticed that would be good to add to the building a release docs. dependencies: pip install networkx pip install sphynx apt install latexmk apt install texlive-fonts-recommended apt...

Virtual instance flattening

2

Blazingmarimba is working on the virtual instances and flattening with those instances. This issue is open to track progress on the virtual instances and flattening with those. We would like...

*Background* Identifiers in verilog are less restricted than EDIF identifiers. They can be longer and contain a wider variety of characters. Verilog names can be escaped to allow any characters...