edif to verilog to edif may lengthen the identifiers.

[thunder-hammer]

Background

Identifiers in verilog are less restricted than EDIF identifiers. They can be longer and contain a wider variety of characters. Verilog names can be escaped to allow any characters except white space.

Edif names can only contain underscores and alphanumeric characters. When the identifier begins with a character that is not a letter, the identifier is prepended with an ampersand '&'

our problem

In our current 1.7 release if an identifier is converted from edif to verilog and back to edif it can grow in length without adding any real meaning. For example:

EDIF identifier: &_identifiied Verilog Converted: &_identified Back to EDIF: &___identified

solutions

I think that a reasonable set of rules when composing to Verilog files would be to assume that.

1. identifiers that start with "&_" are intended to represent a '' escape, thus &_identified will become \identified

if the identifiers are changed with rule 1 then rules 2 and 3 will apply

2. Identifiers ending with "" can be changed to "[]" in the escaped name
3. any '_' that is not in the end or begining can be replaced with '/'

these rules seem to conform with the information available at https://www.xilinx.com/support/answers/1554.html

"When the Cadence SIR2EDF encounters escaped Verilog names (please refer to (Xilinx Answer 2533)), "\L/R " is mapped by the Cadence SIR2EDF netlister to "&l_r". The SIR2EDF netlister also creates a map file, which shows that the identifier "&l_r" is mapped to "\l/r ". Such conversions of backslashes and forward slashes may be fairly common in netlists generated by NGD2VER if user-specified names do not conform to Verilog naming restrictions."