Thomas Schaub

It's not planned to have the pin assignment in the "Readme_Production.pdf" and the schematic (and PCB) of this timecard version is currently not published. Therefore no pinout available at the...

I guess you mean the PPS as output on one of the ANT Connectors? Please check the [Readme.pdf](https://github.com/opencomputeproject/Time-Appliance-Project/blob/master/Time-Card/SOM/FPGA/Readme.pdf). E.g. on ANT4 via AXI GPIO SMA MAP1 you can select with...

Hi @Satoshier comments from the FPGA design perspective: Q1: The UART and PCIe are internally in the FPGA image always parallel available (independent from the HW version you have). But...

We try to keep backwards compatibility of the FPGA image where ever possible. The base functionality should work on all Hardware revisions. So it might be that you see in...

Exactly, it is allowed to use the IP cores as implemented in the bin file. If you have adaptation proposals which have a common interest we can also check if...

There will be soon an update about the open source FPGA version. https://www.opencompute.org/wiki/Time_Appliances_Project on Mar-23, 2022, there will be a call about Open Time Card FPGA

Hi @geerlingguy, hi @wisxxx a first version of the base system (without TOD Slave and PPS Slave) is released: https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/FPGA/Open-Source

> The pinout appears to show that the PCie interface is reduced to one lane. Am I reading it correctly? Not really related to this topic. If you build the...

**Q1:** Your observation is in general correct. The schematics you are reffering does not match with the FPGA readme. The schematics is a beta (should we replace this once? @ahmadexp)...

**Q2:** Theoretically you should see a PPS even without a GNSS module. By default on ANT4 the PPS of the Local Clock from the PPS master is selected. Additionally you...