Teodor-Dumitru Ene

Working with the ASAP7 standard cell library, I noticed the absence of a handful of cells that commonly pop up in arithmetic architecture: ### MUX2 and MUX2I XOR2 is implemented...

[ExpressionForest's __init__() method takes in a node_defs argument as a dictionary](https://github.com/tdene/synth_opt_adders/blob/main/src/pptrees/ExpressionForest.py#L44). [This argument is never used.](https://github.com/tdene/synth_opt_adders/blob/main/src/pptrees/ExpressionForest.py#L157) This could cause issues if a Forest class is defined for a specific operation,...

`node_data` is currently stored across multiple files in a separate folder. #103 raises the point that users of this library need to be able to side-load custom `node_data` for their...

#93 and subsequently #105 overhauled ExpressionTree's __getitem__ to be actually useful. This is not currently documented in any fashion, and should be, as it is a useful shorthand.

v0.4.5 had a diagram generator for classic structures, as can be seen [here](https://github.com/tdene/synth_opt_adders/blob/main/docs/diagrams/sklansky_old.png). This was good. It worked. It was useful. It made things easy to explain. It was discarded...

It has been reported that Verific causes errors when reading netlists generated by this library.

Need to: * [ ] Use Verilator to lint HDL * [ ] Use Verilator to simulate * [ ] Perform language equivalence checking * [ ] Perform logic equivalence...

Currently, the docstrings in this repo fail pydocstyle consistently. This should be fixed.

Adds onto #18 and #23 Is related to, and possibly a subset, of #28 Need to: * Check syntactic validity of generated VHDL code with GHDL * Lint generated VHDL...