Expand support for VHDL

[tdene]

Adds onto #18 and #23

Is related to, and possibly a subset, of #28

Need to:

• Check syntactic validity of generated VHDL code with GHDL
• Lint generated VHDL (with this package?)
• Simulate generated VHDL code with GHDL
• Support technology-specific mapping in VHDL
• Support module blocks in VHDL