TCal

I think I reproduced this hang on the board, building directly in `proj/mnv2_first/` (not in the DSE project). I used Vivado. So if this is what you were seeing, that's...

To clarify, I *only* tried Vivado, and saw the hang there. I will try reproducing using Symbiflow now (my guess is that I'll see the same issue).

Hmm, with Symbiflow with sysclk=75MHz, for me, with several attempts connecting to the board and downloading the firmware, it mostly *does* work, but sometimes doesn't. Working: ``` --============== Boot ==================--...

@ShvetankPrakash I have some general questions. * will this run both in colab and locally? * when running locally, will it exploit available cores to run the jobs in parallel?...

@ShvetankPrakash I encountered this (after installing and entering theSymbiFlow environment): ``` $ python ./vizier_dse.py Traceback (most recent call last): File "./vizier_dse.py", line 2, in import grpc ModuleNotFoundError: No module named...

Hi @ShvetankPrakash , on which Linux release did you test this? I'm hitting various issues, including ``` google-vizier 0.0.5.dev0 requires absl-py=0.7, but you have absl-py 1.3.0 which is incompatible. ```

@ShvetankPrakash , if I forge ahead and try the Vizier run, I see ``` INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations)....

> > Hi @ShvetankPrakash , on which Linux release did you test this? I'm hitting various issues, including > > ``` > > google-vizier 0.0.5.dev0 requires absl-py=0.7, but you have...

Hi Bala, We have been using many sizes of L1 caches, both less and more than 4096.   There was an issue related to size of each "way" in MMU-enabled VexRiscv...

Hi Bala, Well, even if L2 is small, a large L1D cache should still get you benefits if indeed you are seeing L1D misses that can be reduced by having...