taylor-bsg

+ @wsnyder Yes, generally if you grep for "inv", with quotes, those are abstract modules that require parameter instantiation. Those modules should be parsable by verilator, but should fail in...

The repo is https://github.com/bsg-idea/bsg_micro_designs, but this repo contains code that have already been elaborated by https://github.com/bespoke-silicon-group/bsg_sv2v, it is not SystemVerilog. With some work, we could possibly do bsg_micro_designs_sv, which does...

bsg-idea versus bespoke-silicon-group -- basically because github does not have hierarchy, we are trying to avoid having organizations with 100 repos jumped together. We also have an org for external...

So is lint closest to parse only, then? M On Fri, Jan 10, 2020 at 3:27 AM W Snyder wrote: > Verilator has > > - Normal simulation, "-cc --Wpedantic"...

To clarify Alain's issue; it appears that sv-tests is not using his required -sverilog flag to indicate that BlackParrot's files are systemverilog files.

FYI, this looks wrong to me: > # units are fF,kOhm > set_layer_rc -layer met5 -capacitance 315.935 -resistance 0.000003125 This capacitance looks very suspicious. On Thu, Oct 22, 2020 at...

Agreeing with Austin on the subject of implicit wires. This is a bad practice and has been forbidden on my team for 20+ years. M On Fri, Nov 6, 2020...

@maliberty Specifically, we are adding these tests to address a lack of testing of SRAM integration in OpenRoad flow scripts for Sky130. A number of SRAM integration styles are tested....

Compiled using: verilator test.sv --timescale 1ns/1ps -j 14 --main -exe --timing

It seemed like the issue is that only one memory location is keeping track of concurrent values of transport-delay style non-blocking assignments. I tried something like tagging the node with...