Syeda Rafia Fizza Naveed

icon company Usman Institute of Technology icon location Karachi, Pakistan icon location Undergrad | Research Intern at MERL-UIT| RTL Designer | AWS-FPGA

Results 2 comments of Syeda Rafia Fizza Naveed

illegal instruction trap at vlm.v instr

Make sense to me, but then I have 2 more questions: 1) Why **vadd.vv_mf8_rm0_int64_1_0_vl4** is passing (same config but unmasked)? 2) Then, what should be the legal SEWs and EEWs...

illegal instruction trap at vlm.v instr

And what about this test case (vadd.vv_mf8_rm0_int32_0_0_vl8). when lmul=1/8, sew=32 and vlen=8. Is this test scenario is legal or not? Or how we calculate the legal test cases on the...