Results 94 issues of sy2002

* Add to the Monitor OS a `delay` function that takes a 32bit value in R8/R9 and that then uses the cycle counter to syncroneously wait the given amount of...

V1.7

# Marketing Goals V1.7 will be such an awesome release that it is now time to proactively market this project to create a larger community. ## Prerequisites The prerequisites in...

V1.7

This issue steps from this comment: https://github.com/sy2002/QNICE-FPGA/issues/179#issuecomment-719987345 Given a C program like this: ``` int a; void f() { if (a < 2) { a=2; } } int main() {...

V1.7

@MJoergen **YOU ROCK** ๐ŸคŸ ๐Ÿš€ ๐Ÿฅณ ๐Ÿงจ ๐ŸŽ† I truly love your maze game. It is great that you merged it into `dev-vbcc-vasm-fix` because that enables us to release it...

V1.7

Possibly a challenge in the backend (`c/qnice/compiler-backend/machine.c`). Volker said that it is not trivial. I am creating this issue, so that we are not forgetting about it. Right now, we...

V2.0

In the meantime, thanks to the font gfx and sprites - and also the timer - we have so much interessting (and complex) example code to test, that an ability...

V1.7

Make all operating system functions that are working with hardware registers ISR-safe. For context, read https://github.com/sy2002/QNICE-FPGA/issues/109#issuecomment-693892892. ``` isr_mulu isr_muls isr_divu isr_div isr_vga_copyfont ... and more ... ``` **Make sure that...

V1.7

This issue consits of two tasks: 1. Explain the "Monitor-OS" as such and how to use it 2. Write documentation about how to make and publish new OS functions (Monitor...

V1.7

**IMPORTANT**: As of time of writing, this only works on **branch** `dev-vbcc-vasm-fix` VBCC supports ISRs: Test the ISR feature and write a timer interrupt/ISR test for VBCC and put it...

V1.7

One of the basic ideas of QNICE-FPGA is, that it is meant to be highly portable. For sure we are not there, yet ;-) Currently, everything is quite Xilinx specific....

V1.7