Srinivasan Venkataramanan

I like the examples provided such as parser, dataflow etc. Thanks a lot for doing this great work! Say I want to use PyVerilog to query design information such as:...

IVL_UVM test suite (minimal) is now available

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Please see: https://github.com/svenka3/ivl_uvm As suggested by developers of this wonderful repo earlier, I am keen on adding these tests to sv-tests thrid_party and more importantly making it regression friendly. I...

Chisel-formal - apps as starting point

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During today's CHIPS alliance event, Jack presented Chisel and introduced this repo to me. Based on our Q&A in that forum, I am adding this suggestion for this community. A...

Support `checker`

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Thanks for taking the time to report this. What would you like added/supported? > checker..endchecker - LRM added these as containers for SVA. Though it has few additional features/benefits, a...

VerilogLintBear - minor fix for Verilator lint

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I am trying https://pypi.org/project/VerilogLintBear/ with latest Verilator and I believe the regexp needs enhancement to add column number parsing. Below is what I had to fi to get it working:...

VCD to WaveDrom converter

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Hi, Is there a VCD to WaveDrom converter available? Thanks Srini

Also, you have memory leaks in your code. The result from `strdup()` and `malloc()` need to have `free()` called to release the memory. The argument iterator is not released correctly...

I would switch the code from using `tf_dofinish()` to `vpi_control()` so you are only using the more modern VPI calls. The tf/acc routines are completely obsolete and have not been...

Need unit tests for new semaphore implementation in IVL_UVM. Reference: https://github.com/steveicarus/iverilog/discussions/642 Ref: SV LRM IEE 1800-2012 Section 15.2

[dv] dvsim -t xrun enhancement

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Today I tried running OT on a different laptop with Cadence XLM tool. I made small mistakes (call it rusted due to out of touch with OT flow) and one...