VerilogLintBear - minor fix for Verilator lint

[svenka3]

I am trying https://pypi.org/project/VerilogLintBear/ with latest Verilator and I believe the regexp needs enhancement to add column number parsing. Below is what I had to fi to get it working:

Old code:

@linter(executable='verilator',
        output_format='regex',
        use_stderr=True,
        output_regex=r'\%(?:(?P<severity>Error|Warning.*?).*?):'
        r'.+?:(?P<line>.+?)  (?P<message>.+)')

New/fix:

@linter(executable='verilator',
        output_format='regex',
        use_stderr=True,
        output_regex=r'\%(?:(?P<severity>Error|Warning.*?).*?):'
        r'.+?:(?P<line>.+?):(?P<column>.+?): (?P<message>.+)')

Without that fix I got error as:

ValueError: invalid literal for int() with base 10: '6:17:'

With that fix, it is happy and shows:

[DEBUG][17:47:18] Running bear VerilogLintBear...
[DEBUG][17:47:18] Running 'verilator --lint-only /home/srini/proj/AsFigo/git_af_sv_lint/sv_tests/af_sv_mod.sv'

../sv_tests/af_sv_mod.sv
|   6| ··assign·bits_8·=·bits_4;
|    | [NORMAL] VerilogLintBear:
|    | Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'bits_4' generates 4 bits.
|    | *0: Do nothing
|    |  1: Open file(s)
|    |  2: Add ignore comment

Now it is not clear how to submit this patch. Any comments please?

Thanks Srini

[svenka3]

@Adrianzatreanu in case you are tuned in here, please suggest.