Stefan Mach

The issue seems to be that the pipeline is not flushed upon CSR write to frm, i.e. the instruction decoded at t##0 does not see the updated CSR (and should...

This bug is related to #169 where the change to `frm` in the previous cycle is not seen by the `fcvt` instruction following it. Leaving this open until #169 is...

I agree that a struct would be the cleanest way of configuring the FPU, and it was the desired option during the design, too. Having named struct members is definitely...

Yeah let's try that. In general, if having parameters at the top level is an issue, an additional option could be to provide an alternative version of the top module...

Had a deeper look into this, and given SystemVerilog's (and EDA tools') limitations it's a miracle any slightly more complex structure can be even generated as is currently.. The main...

Hello! Yes, the div/sqrt unit is an iterative block, so, unfortunately, timing cannot be improved beyond a certain point by adding input/output registers (as these only alleviate the relatively long...

Yes, the code can be synthesized as-is in Synopsys DC. For sure DC version `2019.03` and above are supported.

Hi, could you provide a code snippet with your instantiation of the FPU with the parameter list used? That would help to reproduce your config and identify whether something goes...

Hello and thank you for using PULP and taking some time to run tests! I'll have a detailed look at the results of your test runs but here are some...

We know of the DIVSQRT unit not faithfully performing the *round to nearest, tie to even* rounding mode (which unfortunately is the default). This can lead to results being off...