Illegal Instruction Exception not Raised - Dynamic Rounding Mode

[shetalani]

RISC-V Specification:

• "Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm."
• "Rounding modes are encoded as shown in Table 11.1. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm."
• "If frm is set to an invalid value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic rounding mode will raise an illegal instruction exception."

Issue Description:

An illegal instruction exception is not raised for the case when a floating-point instruction uses a dynamic rounding mode while the frm is set to an invalid value.

Example:

As shown below, the instruction 32'hc011f1d3 (fcvt.wu.s x3, f3) is decoded at time point t##0 where rm field has the value 111, and frm has the value 101 (written by a previous instruction), with no illegal instruction being flagged, as illegal_insn_dec is de-asserted.

---

Product: OneSpin 360 DV-Verify App: RVV Tool's version: 2019.2.2

[stmach]

The issue seems to be that the pipeline is not flushed upon CSR write to frm, i.e. the instruction decoded at t##0 does not see the updated CSR (and should actually stall until t##1). We'll have a look.

[pascalgouedo]

Resolved with PR #801