sai krishna pidugu

@ASintzoff Please find the [setup](https://github.com/openhwgroup/core-v-verif/pull/1254) that I used to set RISCOF dv-arch-test suite.

with updated version of spike issue got resolved and I am closing this issue.

@JeanRochCoulon I faced issue while I was using commit id: e93b9cbbbcd3ad0a02ae298e9f1a2d98d3ac0153,but with latest version [spike 1.1.0](https://github.com/riscv-software-src/riscv-isa-sim/releases/tag/v1.1.0) issue got resolved.

@JeanRochCoulon fmul test is failed on VCS also, currently I am using verilator-4.110 version.

Hi, I am also trying to generate waveform in verilator for cva6 in core-v-verif environment. please let me know if this issue got resolved and suggest how to enable generation...

@RanjanThales

Hi @MikeOpenHWGroup, please find the steps to replicate PMPCFG0 issue as mentioned below. 1.git clone https://github.com/spidugu444/core-v-verif.git 2.git checkout pmpcfg0_issue 3. Command to run PMPCFG0 test **source cva6/regress/smoke-tests.sh** 4. Test file...

**PMPCFG[0]- PMPCFG[1] : while writing any random value it is always reading the value that we write after reset.** As per riscv privileged specification   The lock bit is...

@RanjanThales