SPCL

Neural Code Comprehension: A Learnable Representation of Code Semantics

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Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

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DaCe - Data Centric Parallel Programming

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Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

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SeBS: serverless benchmarking suite for automatic performance analysis of FaaS platforms.

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Python interface for MLIR - the Multi-Level Intermediate Representation

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FPGA acceleration of arbitrary precision floating point computations.

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A Data-Centric Compiler for Machine Learning

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Deep Learning for Post-Processing Ensemble Weather Forecasts

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BLAS implementation for Intel FPGA

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