Somya Dashora

comment aligment

2

**Test case** Either the comments should be aligned by formatter or already aligned comments should remain intact. The below code was already aligned. ```systemverilog // Input to the formatter, preferably...

Type of issue: bug report Impact: Compliance with the privilege spec. From privilege spec (20190608) section 4.3.1: ``` For non-leaf PTEs, the D, A, and U bits are reserved for...

How to add custom CSR definition in whisper

2

I wanted to add my custom CSR like MRAC in Whisper, how can i do that? Also accessing MRAC via _peek c 0x7C0_ gives **Failed to read CSR: 0x7c0** How...

I was trying to generate a testcase for 4 threads for S/U mode. I used the following command. `python3.6 run.py --target=rv64gc --test=riscv_rand_instr_test --iss_timeout 20 --gen_timeout 7200 --output rv64_riscv_rand_instr_test --isa=rv64gc --mabi=lp64`...

In riscv-dv at commit 5a79a54f8330c904eae98e51be55bbb55ac30c82 The following command was run to generate mmu stress cases ``` shell python3.6 run.py --target=rv64gc --test=riscv_mmu_stress_test ``` These were the generated test cases in out/asm_test...