PTW: Non-leaf PTEs with D/A/U==1 are reserved

[somyadashora]

Type of issue: bug report

Impact: Compliance with the privilege spec.

From privilege spec (20190608) section 4.3.1:

For non-leaf PTEs, the D, A, and U bits are reserved for future use and must be cleared by software
for forward compatibility

https://github.com/riscv/riscv-isa-manual/blob/b6480da0db0c428a8ab29b65cae693041cd3e874/src/supervisor.tex#L1652

What is the current behavior? No page fault exceptions when non-leaf PTEs have D/A/U bits set.

What is the expected behavior? page fault exception should trigger when non-leaf PTEs have D/A/U bits set.

Potential change is required at this location : https://github.com/chipsalliance/VeeR-ISS/blob/a6fabee95de4aa0f3e9b1ff97d02d1d7af62d3bd/VirtMem.cpp#L241

Related Issue in other ISS (Spike): https://github.com/riscv-software-src/riscv-isa-sim/pull/752 https://github.com/riscv-software-src/riscv-tests/issues/352 Fixed here: https://github.com/riscv-software-src/riscv-isa-sim/commit/a9c10bdaee4d88ca89d15565f08701ad0783c974

Also is this ISS currently being maintained here, or is moved to some other location or is nobody maintaining it?