silabs-oysteink
silabs-oysteink
## PUSH and POP type instructions marked as illegal instructions ### Type * Functionally incorrect behavior ### Steps to Reproduce 1. Use my fork of core-v-verif: [email protected]:silabs-oysteink/core-v-verif.git 2. Checkout my...
The current version of the user manual describes the format from the tracer that used to be defined in cv32e40x_rvfi_trace.svh. This has been removed (PR #597) and instead the tracer...
The spec states: "Horizontal synchronous exception traps, which stay within a privilege mode, are serviced with the same interrupt level as the instruction that raised the exception. Vertical synchronous exception...
If mcause.minhv is set when we execute an mret, we shall not restore the pc to the contents of mepc, but instead do a pointer fetch M[mepc] as for the...
Currently, a CLIC pointer that arrives in WB will not signal wb_valid, and RVFI is not notified of the pointer. Similarly, split LSU accesses only signal wb_valid for the last...
When single stepping is enabled, the controller will take a pending-and-enabled interrupt and enter debug mode. This happens when the controller signals 'irq_ack == 1', which currently is set for...
For vectored CLIC interrupts, the following events happen: 1. IRQ becomes pending 2. IRQ is taken, irq_ack=1 3. Pointer is fetched 4. A jump is performed to the loaded pointer...
The debug state fsm currently does not allow the transition from debug_havereset to debug_halted (see image).  The controller needs an update to ensure the transition will be possible. If...
## Trigger CSR reset values The reset values for tdata* CSRs are currently not frozen. These values must be reviewed after clarification in the spec has been done.
If a CSR has a field set to WARL, and reset value specified as 0, what is the correct behavior? Example: A core will only support mcontrol6.action = 1. The...