silabs-mateilga

> Ah, forgot to mention the path. The commands must be ran from: core-v-verif/cv32e40x/sim/uvmt/

Ah, apologies, I sometimes forget how much of the environment is "just there". export CV_SW_TOOLCHAIN=/tool/gcc/riscv32-embecosm-gcc-centos7-20211031 export CV_SW_PREFIX=riscv32-unknown-elf- export CV_SW_VENDOR=unknown export CV_SIMULATOR=xrun export CV_CORE=cv32e40x

I'm unsure of what the specific problem is, but here is the latest documentation of the environment variables required. https://github.com/openhwgroup/core-v-verif/tree/master/mk#required-corev-environment-variables

The difference happens at the retirement of instruction 38861. I unfortunately don't have the opportunity to dig further in to this now, I'll have a look first thing Monday morning....

@eroom1966 The following is the output from the test: `UVM_ERROR @ 2599926.300 ns : uvme_cv32e40x_core_sb.sv(381) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 38861, pc: 0x00020c8e, csr: mstatus, rvfi = 0x00001888, rvvi =...

[test_program.zip](https://github.com/openhwgroup/core-v-verif/files/8108359/test_program.zip) @eroom1966 Extract these files to [your_results_path]/results/xrun_results/default/corev_rand_interrupt_wfi_mem_stress/27/test_program/ Run the second command in the top post here. (make test ...) This will allow you to at least run the same instruction...

I highly doubt we will see a failure with a seed that fails on one xcelium version on another xcelium version. As I mentioned, the easiest would be if you...

related issue solved

@eroom1966 I think this issue is deprecated now, I'll get Øystein to close it, and we'll open new issues if there is still something here. That said, the RVFI interface...

@silabs-hfegran I am not aware that any effort has been made to create an assertion and/or directed test to cover this.