silabs-mateilga
silabs-mateilga
@MikeOpenHWGroup This problem is in documentation only, and is therefore only confusing, not blocking. I'm not sure if it is necessary to see a testcase, but the signal is driven...
Item 3 is solved with PR #1307
That is item 3 for 40x. I'll try to get an overview of the other issues today.
@eroom1966 thanks, the PR is merged now. Does this cover all the issues listed under 40x? We are going to merge (cvverif) 40x to 40s as soon as possible, to...
@eroom1966 I've been running a few tests on your latest commits, and have found two issues. 1. misa bit 1, "B", mismatch for some configurations reproduceable by running "make test...
Hi Lee, sorry for the delayed response. When PR 1314 is approved, you should be able to continue work on 40s. This is by no means a finished or steady...
@Silabs-ArjanB please add this issue to the 40s list: https://github.com/openhwgroup/core-v-verif/issues/1326
@Silabs-ArjanB 40s item 9 is resolved
This could be as simple as the test not creating this scenario, or the tests failing on other issues before this. -Marton From: Lee Moore ***@***.***> Sent: torsdag 23. juni...