Shinya T-Y

function integer

3

The current parser may not be able to parse the code as below. ```verilog function integer funcname; input invalue; // ... funcname = 0; endfunction ```

See #77

In some hardware designs, initial statements are utilized to set initial values of registers and memory cells. However the current dataflow analyzer in Pyverilog does not support the initial statement...

Explicit latency constraint between two stream objects which accesses to external resources outside of the stream.

1

thread.stream has some external operators to access outside of the stream pipeline, such as ToExtern/FromExtern, read_RAM, write_RAM. Additionally, RingBuffer and Scratchpad uses on-chip RAM as a random access buffer. The...