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                                            Mohamed Shalan

Update Litex mgmt soc

@tmichalak 1) LiteX generated Verilog HDL contains inline initializations for several registers. These initializations are not ASIC friendly. In ASIC they have to be initialized using a Reset signal. In...

Update Litex mgmt soc

@tmichalak Please check: https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/verilog/rtl/mgmt_core.w_rst_init_modification.v Regarding the new debug bridge, I understand that it is not yet FPGA validated. Was it verified in simulation? Also, is there any documentation for how...