anasymod
anasymod copied to clipboard
sgherbst
A framework for FPGA emulation of mixed-signal systems
The buildkite CI test for this repo, which used to be here: https://buildkite.com/stanford-aha/anasymod appears to be long dead and maybe never used at all. So, in the interest of efficiency,...
It would be awesome if you could support using the [SymbiFlow open source FPGA toolchain](https://symbiflow.github.io) as an alternative to Vivado. As the SymbiFlow project would be interested in have some...
I would highly recommend using [the edalize library](https://github.com/olofk/edalize) from @olofk to provide an API to various EDA tools like Icarus or Xilinx's Vivado. If used correctly this would potentially enable...
This information is already in simctrl.yaml, so it should be possible to avoid having the user re-enter this information in sim_ctrl.sv (perhaps via auto-generated files they can `` `include ``)
Even if firmware is partly hand-written, it would be nice if the UART interpreter were still auto-generated, along with get/set commands for signals in simctrl.yaml.
This would be useful to reduce turn-around time for running UART-based tests, if the FPGA is already programmed.
This would be useful to reduce build times, and also to debug certain build problems.
Sometimes projects contain ``*.v`` files that use SystemVerilog syntax, but cannot be renamed. In Vivado, one way to solve that problem is with the following command: ```tcl set_property file_type SystemVerilog...