Provide method to treat *.v files as SystemVerilog files in Vivado

[sgherbst]

Sometimes projects contain *.v files that use SystemVerilog syntax, but cannot be renamed. In Vivado, one way to solve that problem is with the following command:

set_property file_type SystemVerilog [get_files -filter {FILE_TYPE == Verilog}]

This upgrades Verilog files to SystemVerilog. I prefer not to match on the file extension *.v, since that might inadvertently switch some VerilogHeader files to SystemVerilog, which could break compilation.

The main questions about integrating this feature are: (1) how the user should enable/disable it, and (2) whether it should be enabled or disabled by default.

[sgherbst]

Notes:

• This should be applied to both anasymod/emu/vivado_emu.py and anasymod/sim/vivado.py.
• Some extra TCL code needs to be added to prevent the command from failing if there are no Verilog files.