Jiuyang Liu

opps, plz make the following PRs to be small ;p

sorry for the delay, I was out of office these todays. Will do it 8pm cst today.

Maybe `chirrtl`(the firrtl-like IR directly generated by chisel) could be a good IR to implement? From a firrtl transform developer view, I think a LLVM-like transform flow manager and correspond...

> You mean as a conversion input/output in llhd-conv? I think chirrtl can be the input to llhd, or with few firrtl transform to keep the hardware same as it...

> It seems that the plan over at Chisel is to eliminate CHIRRTL altogether (freechipsproject/firrtl#727). Yep, chirrtl will be eliminated finally, I means only absorbing few transforms, shift left as...

This PR breaks playground regression CI in https://github.com/chipsalliance/playground/runs/7890002567, which should be fixed in the RC.

> @mwachs5 this sounds like `LazyModule`'s `InModuleBody`. For user-API this is `InModuleBody`, but for library writer, it is the [instantiate](https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/diplomacy/LazyModule.scala#L273-L329) function. > @jackkoenig That sounds a lot like aspects to...

Sorry I forgot that PR... Need I rework on that?

@ekiwi would you mind cherry-picking `chisel.std` definition in build systems(sbt mill) firstly, creating another PR, and #2518 can directly use that?

I just encounter this when demonstrating FIRRTL `vlsi_mem_gen` hours before! As you can see from https://github.com/chipsalliance/firrtl/blob/8bca41522cdc4b8ff69734cd159ce29f984d3290/src/main/scala/firrtl/passes/memlib/ToMemIR.scala#L18-L20 MemIR is not a part of FIRRTL IR, it is more like a WorkingIR...