Jiuyang Liu

Yes, I'm writing a wrapper, by extraction all Edge paramters, reconstruct a Top MultiIOModule, yes, it's a liitle ugly but seems works now. After finishing this, I will give a...

I have such problem these days, and I got an idea(a not pretty way to solve this), but technologically, it works, I wonder if there is any elegant way to...

Currently idea to do this implementation: 1. annotate signal required to be peek/forced. 2. use firrtl transform to add `/**verilator public**/` attributes, which need freechipsproject/firrtl#1172 3. add chiseltester API to...

Yes I'm going to PR it after I finish #156

Currently, my implementation is generating `Exception`, put them into an buffer, for each cycle, if the element inside this buffer is non-empty, simulator will stop. and let ScalaTest collect this...

Maybe we can maintain map of (chiselElabroatedCircuit -> verilatorModelFile) as annoation? Let user decide how to cache these thing. Sent with GitHawk

> Why do we need this instead of just letting CIRCT parse the .fir and .anno.json? Currently, CIRCT can directly parse fir+annos. However I think this PR is still necessary:...

sbt is still using `protocjar` from `os72`, which seems not being actively maintained anymore. ``` lazy val protobufSettings = Seq( sourceDirectory in ProtobufConfig := baseDirectory.value / "src" / "main" /...

I think so. This will lead to uncertain result to a FIRRTL circuit.

related to chipsalliance/firrtl#1062