Jiuyang Liu comments

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                                            Jiuyang Liu

Pass FIRRTL annotations into `CIRCTConverter`

@SpriteOvO Please use 'Please Merge' label to ask bot merge it. A label is also required.

[Panama] Request to bind InstanceGraph API from CIRCT.

Reopen it since #3798 only provide a Binding w/o user-level API.

Make Chisel5 generate parameter in Verilog

I don't think this will happen in the near future. However Chisel supports embed Parameter embedded as `Property` inside MLIR.

Add Incoming/Outgoing as alternatives to IO

And another required thing might be providing a `Decoupled` and `Valid` equivalent type, and even deprecate the `coerced` one.

Add Incoming/Outgoing as alternatives to IO

> What would an explicit `Aligned` do? Isn't that a no-op? How about provide a semantic: ``` Aligned(Flipped(MyThing())) Aligned(Aligned(MyThing())) ``` Both equal to ``` Aligned(MyThing()) ``` `Aligned` will ignore the...

Differences Between := and :<*= involving Analog and DontCare

Basically I think this is a pitfall in chisel type system, in chisel it runtime modify the chisel type when a wire is connect to other wire. Basically I think...

Bundle literal construction outside test() is not allowed in Chisel 5.0.0 (works in 3.5.4)

Please submit this bug report to chiseltest.

BoringUtils.bore does not work properly in `when` scope

OK this is certainly a bug. Like declaring register or memory inside when block. In the boring utils case, I personally think it should be forbidden.

BoringUtils.bore does not work properly in `when` scope

Just noticed, did we have same issue for `Mem.read`, `Mem.write` in `when` block sometime ago?

BoringUtils.bore does not work properly in `when` scope

FYI, https://github.com/llvm/circt/issues/1561 may also relate to this issue.