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seandextercrevinn

Trying to change read interface to AXI4, getting elaboration errors when generating verilog

Changing Line 36 instead to: ``` - val read = Flipped(new AXIStream(DMATop.readDataWidth)) + val read = new AXI4(DMATop.addrWidth, DMATop.readDataWidth) ``` ... seems to have allowed it to compile. Please advise...