Seyed Alireza Damghani

@HMoein87 : @ArashAhmadian is one of UoT students working on improving the regression test. He has recently faced the same issue you have been working on last semester. In [64-16bit-fixed-JACM.v.txt](https://github.com/verilog-to-routing/vtr-verilog-to-routing/files/6526667/64-16bit-fixed-JACM.v.txt),...

@hzeller - I am facing a segfault (without any error message) using the `read_systemverilog` command for a new HDMI benchmark that I added in this PR (path to the [benchmark](https://github.com/sdamghan/vtr-verilog-to-routing/tree/SystemVerilog_UHDM_VTR/vtr_flow/benchmarks/system_verilog/hdmi):...

Thanks @hzeller. This PR is ready for merge. I would appreciate any comments or reviews if you are interested. A few points I should mention: 1. @vaughnbetz - We previously...

@vaughnbetz - According to the CI failure discussed in #2124, I removed the Surelog and Yosys-F4PGA-Plugins submodules from the VTR repository. Instead, I added them as external projects to the...

Hi @Sun1927 - not sure if you have still this problem, but you can compile the Odin-II in debug mode by going into the "VTR_ROOT/ODIN_II" and then run "make debug"....

@vaughnbetz not sure why this is left, I was not aware of the progress of this PR. Will investigate more in the future

The CI failure is due to a memory leak created from the new operator in libraries. See below: > Note: the memory leaks are inside the `XmlReadArch` routine, which are...

@vaughnbetz - there are a few weird memory leaks in the libarchfpga source code, which are caused by runtime memory allocation for expanding vector size or emplace back to it....

Thanks @vaughnbetz, for the suggestion. I just figured out the issue source; it seems like by dynamic memory allocation for the `t_arch` struct, the program would result in some unexpected...

@harpreetbamrah would you please have a look?