Seyed Alireza Damghani
Seyed Alireza Damghani
This PR provides the initial support for the SystemVerilog and UHDM plugins designed for Yosys. The Surelog and Yosys-F4PGA-Plugins repositories are added as submodules to the VTR repository. Both Surelog...
#### Description This PR adds an ability to `libarchfpga` to generate a file that includes the declaration of non-vtr-primitive complex blocks (complex blocks that are defined by users, not adder,...
#### Description In this PR, the Yosys script for the Yosys+Odin-II is updated to perform the synthesis for basic operations by Yosys. Then Yosys generates the BLIF file with unmapped...