Seyed Alireza Damghani

@aman26kbm - Would you please share a short summary of the results and your thoughts here? If there is no more roadblock or issue, we can move forward and merge...

We temporarily suspend this PR to provide appropriate solutions for the bugs mentioned above.

Hey @alirezazd and @poname , this PR is about upgrading the Yosys+Odin-II front-end by using more Yosys side by performing some simple mapping and postponing technology mapping of the memory...

@poname - considering the Yosys recent changes on memory blocks, you would be required to consider upstreaming the VTR-Yosys for Odintechmap and provide the support for newly added components, as...

It seems some repositories, like googletest, are recursively used with various versions in the Yosys UHDM Plugins Integration. For instance, we got `googletest @ 8d51dc5` inside _Surelog/third_party_ and `googletest @...

Closing this issue as the support is added in PR #2068, and documentation will be updated in PR #2139

@aman26kbm - thanks for raising this issue. As I mentioned earlier, the Yosys-generated coarse-grained BLIF files miss a few internal connections in deep submodules (compared to the top module). I...

Great @aman26kbm - these are helpful findings; let us go through the detail. I will provide more updates once we find the issue root. Update: @aman26kbm - I double-checked the...

> A few other things to mention that could be relevant: > > 1. There are some ROMs in the design. They are RAMs with write_enable and data_in tied to...

@hmoein87 Would you please have a look at this?