Martin Schoeberl comments

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                                            Martin Schoeberl

Mem seqRead specification out of date

Very good. That fits for memories available in current FPGAs: you need to use a register in the input (address, data, wren). The output register is optional. Cheers, Martin On...

Register size inference

If the bit width of an UInt is not part of the type (has no meaning in Reg(UInt(n))) why is the register width than 1? Could be 0, or anything?...

Register size inference

Is there a use case for creating a register with Reg(T) when the size is reduced to a single bit? The current behavior is at least surprising, in the worst...

why the code of VendingMachineSwitch.scala in the tutorial generate if-else statement instead of case statement

You need to include chisel3.util._ and use a switch. See an example here: https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/SimpleFsm.scala

Support for ready/valid

When you implement some HW that uses ready/valid handshake it would be good to test what happens on trying to push data as fast as possible. I guess this is...

Possible bug in MemFifo in fifo.scala

Sorry for the late answer. Would it be possible to write a small test that shows the bug? And better place an issue into the original source in: https://github.com/freechipsproject/ip-contributions

Build mobi version for Kindle

I don't know how to do this. Could you help?

Writing should have priority over reading

Can you explain the difference? These are all concurrent statements.

coursier error

I am not sure what you are meaning here. We are not using the jupyter notebook. Maybe I should delete it.

I’ve committed the version with the issue in: https://github.com/t-crest/soc-comm Run it with: sbt "testOnly s4noc.PerformanceTest" Thanks for looking into it. Cheers, Martin > On 26 Sep, 2022, at 15:25, Kevin...