scarv-cpu
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scarv
SCARV: a side-channel hardened RISC-V platform
Implement the Bitmanip `xperm.*` instructions. Currently blocked by upstream bitmanip since the instruction has no opcode. - [x] Decode - [x] Execute - [ ] Verfication
Add [FuseSoC](https://github.com/olofk/fusesoc) support.
A library / single header which contains intrinsics, constants and functions related to managing the core. - [x] CSR Access functions. - [x] Machine-mode timer control and access. - [...
Tracking the status of the finite field instructions: `mask.f.mul` and `mask.f.aff`. - [X] Decoder and operand selection RTL. - [X] Execute stage operation selection / routing. - [ ] Masking...
- Currently, the masking ISE is implemented on the `scarv/xcrypto/masking-ise` branch only. - This has/will diverge heavily from the `scarv/skywater/main` branch. - The masking ISE functionality can partially be copied...
Currently, all control flow changes have a **5** cycle penalty, since they wait until the instruction reaches writeback before triggering the change. Two improvements are possible within the scope of...
Hi there! Some tools require wires and regs to be declared before used. This PR fixes this, without intending to change the functionality of the module. Thanks! Flavien
