rs-dhow
rs-dhow
@KA7E and anyone else working on the packer. First, I was happy to find: https://docs.verilogtorouting.org/en/latest/tutorials/arch/equivalent_sites/ We will use this feature. #### Proposed Behavior Currently, we don't implement programmable constants or...
The .net file may specify an "internal feedback" path in a CLB. This means an FLE output has been selected in a "mux" or "complete" construct all inside one block....
Under vtr... there is a file rr_gsb.cpp which has the function calls sort_chan_node_in_edges(3 args) and sort_ipin_node_in_edges(3 args). Both have an initial loop which collects in-edges into a std::map, then a...
Assume an architecture with CLBs. Each has multiple FLEs. Each FLE has a 2xLUT5 mode, i.e., 2 LUT5s share 5 inputs and have separate outputs. There are other modes not...
If .net and .route is such that one net appears on multiple IPINs on one block, then OpenFPGA (repack and/or bitstream) may deviate from the connection specified in these files....
In the pb_type_annotations section of openfpga.xml, there is a property physical_pb_type_index_offset which can be used as follows. An FLE may have a 2xLUT5 mode with 2 physical FFs. When it...
On larger designs, bitstream generation appears to change the routing. The bits were read back in and the routing tracked. No net ever changed the set of OPINs and IPINs...