repacker/bitstream generation changes internal block muxing to different IPIN

[rs-dhow]

If .net and .route is such that one net appears on multiple IPINs on one block, then OpenFPGA (repack and/or bitstream) may deviate from the connection specified in these files. This may affect timing.

IPINs don't change. The choices on "mux" and "complete" muxes inside the block may change.

Any of these would be preferable:

1. Always follow .net and .route faithfully.
2. Have a "faithfulness" option.
3. Write back out .net and/or .route to indicate what OpenFPGA did.

Quiet/unannounced changes can lead to confusion during detailed debug and/or timing surprises.

Thanks

To Reproduce Steps to reproduce the behavior:

1. Clone OpenFPGA repository and checkout commit id: <The problem commit id>
2. Execute OpenFPGA task or your own example:
3. See error

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