Román Cárdenas Rodríguez

While working on #200, I've been thinking on how to provide this functionality. I propose the following approach: - Remove weak symbols in linker file (i.e., the `PROVIDE` directives) for...

I guess that you can implement a "mask-like" behavior with two or more PLIC contexts. In this way, you can use one context for only enabling all the interrupts in...

# Different approach: do not use generics nor enums at all in `mcause` and `scause` I think the current proposal might become hard to handle for developers, as they now...

Thanks for the feedback @rmsyn ! I implemented my alternative approach in the [`riscv-pac2` branch](https://github.com/rust-embedded/riscv/tree/riscv-pac2). Please take a look and let me know what you think. Personally, I feel like...

So I think the new `riscv` version looks good (still needs some testing etc.) BUT... it's time for `riscv-rt` and the interrupt/exception handlers. We need to provide an out-of-the-box solution...

I found some time to keep working on this. In the new commit, the following code: ```rust #[pac_enum(unsafe PriorityNumber)] #[derive(Clone, Copy, Debug, Eq, PartialEq)] enum Priority { P0 = 0,...

It already creates the interrupt vector table. However, I think we should discuss the new approach with the @rust-embedded/tools team to align `svd2rust` with the new structure

Exciting times! I think the `riscv` ecosystem will improve a lot with #222 and this PR. I will wait until #222 is solved and merge the outcome, so we can...

I updated this PR to use the new features coming from #222 . An additional change is that I moved the macros to `riscv` instead of `riscv-pac`. As now `riscv-pac`...

The thing is that it still complains for RISC-V targets :/