Román Cárdenas Rodríguez
Román Cárdenas Rodríguez
https://github.com/beerfactory/hbmqtt/blob/031580a3fcb014e2752fa07c021781a0486684f8/hbmqtt/broker.py#L394-L396 When authentication fails, the number of connections to the broker does not change, so every failed attempt is counted as a connection. I suggest to change that if block...
Hi! Congratulations, I really like this bot. I have a functionality suggestion. It would be nice to add a new mode for transcribing audios only when a group member cites...
Hi! I think it would be nice to add a `DelayUntil` utility to delays. In this way, we can have actual periodic tasks, regardless of the time consumed by a...
I've been studying the `riscv-rt`, `e310x` and `e310x-hal` crates for a while, and I'm currently exploring different interruption modes. As far as I know, `riscv-rt` leaves you the `MachineExternal` function...
The [Software-Level Interrupt Controller (SLIC)](https://github.com/romancardenas/riscv-slic) is a software interrupt controller that aims to mimic the PLIC but using a single interrupt source. It currently works for the CLINT peripheral, but...
From the documentation, I assume that the `set_compare` method aims to schedule an interruption for a given time instant. However, in my use case, there is a chance that I...
As mentioned in #815 , it would be very useful to allow backends have additional configuration parameters. This is specially necessary for RISC-V, since there will be different interrupt controllers...
As discussed in the previous meeting, now that RTIC v2 targets multiple architectures, some items seem too biased toward Cortex-M microcontrollers. One of these elements is `rtic::export::Peripherals`. For instance, the...
**Describe the bug** I am not able to flash my binary using `probe-rs` over a fe310g002 RISC-V target. However, GDB works fine. **To Reproduce** Steps to reproduce the behavior: 1....
The @rust-embedded/risc-v team is preparing a few changes for the RISC-V ecosystems. One of these changes is the [`riscv-pac`](https://github.com/rust-embedded/riscv/tree/master/riscv-pac) crate, which will hold all the interrupt-related traits any RISC-V PAC...