Román Cárdenas Rodríguez

icon indicating a website link https://blogs.upm.es/lsi/roman-cardenas/ icon indicating an email [email protected]

icon company @greenlsi icon location Madrid icon location Assistant Professor at the Technical University of Madrid (UPM). My research interests include Modeling and Simulation applied to the IoT domain

Results 190 comments of Román Cárdenas Rodríguez

`riscv-rt`: Support for vectored mode interrupt handling

I successfully ran an example on QEMU using `MachineTimer` and `MachineSoft` interrupts in vectored mode. For each interrupt source, an independent trap handler is added in the final binary: ```asm...

`riscv-rt`: Support for vectored mode interrupt handling

I tested this with my SLIC crate, which exploits nested `MachineSoft` interrupts to have an interrupt-driven program (e.g., RTIC). So hopefully you will face no issues.

`riscv-rt`: Support for vectored mode interrupt handling

**TO DO LIST** - [x] I would love to skip `_start_trap` at all and leave it only for exceptions. We could use the `DefaultHandler` to do this: https://github.com/rust-embedded/riscv/blob/aca641040c5bd3ef856bee94f2db0e235d6bb317/riscv-rt/src/lib.rs#L478) - [...

`riscv-rt`: Support for vectored mode interrupt handling

New changes to `riscv-rt`: - Now, when an interrupt is detected, `_start_trap_rust` calls `_dispatch_interrupt(interrupt_number)`. This does not really change anything from previous versions, but we are now closer to accepting...

`riscv-rt`: Support for vectored mode interrupt handling

The PR is good to go. @rust-embedded/riscv please take a look.

force-amo: allowing AMOxxx instructions for riscv32imc

This PR solves #56

`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)

I noticed this error. It looks like a weird issue between the Rust compiler and LLVM. Perhaps it does not propagate the extension flags correctly? In any case, it produces...

`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)

The previous version of `riscv-rt` used pre-compiled blobs linked at compile time. Now, we use inline assembly, and the Rust compiler includes the assembly code in the build process. I'll...

`riscv-rt`: LLVM raises spurious errors in release mode for instructions of ISA extensions (e.g., M or E)

#176 provides a provisional patch to remove these spurious errors. It will do the trick while LLVM solves this issue

`riscv-peripheral`: add standard peripherals

Good catch, not sure about how to proceed with this. I suggest you implement the peripheral for your board, so you can test it. Then we can use feature flags...