rmsyn

> I am not sure whether it is worth it or not. Notice that feature gates become way more verbose. So, I A/B tested the changes in this PR and...

> Exported macros need to reference cfg(target_arch = ".."). So, maybe just the exported macros get `cfg(target_arch = "..")`, and the rest can use the existing `cfg(riscv*)`? If so, I...

I don't know why the `clippy` checks are suddenly failing now. I run the checks locally from CI runner: ```bash cargo clippy --package riscv-rt --all --features=s-mode -- -D warnings ```...

> This patch fixes the link error (and gdb backtraces) Just confirmed that this fix works, and the problem still exists on hardware + QEMU. > seems like the wrong...

> That loses some flexibility within oreboot. If you look at the `jh71xx-hal` code, all of the functions for DDR bring-up are still callable individually. Meaning, instead of just calling...

> However, there is no clear indicator that this is related to the header rework. Except there is! I did a git-bisect on the recent commits, and wouldn't you know...

> That loses some flexibility within oreboot. Here is a commit showing doing each part of `Ddr::init` manually: https://github.com/oreboot/oreboot/commit/ff8f439a37aa0e0ba291ceebb5d1631892760924 > To work on that code, one would need to clone...

> I will merge this next week, cause I have a few new features to implement. Sounds good. Let me know when you're ready for me to rebase on your...

> it makes sense to me that the Interrupt and Exception enums are in riscv::interrupt instead of riscv::register That makes sense to me, too. Really either one can work, because...

> I implemented my alternative approach in the [riscv-pac2 branch](https://github.com/rust-embedded/riscv/tree/riscv-pac2). After an initial review, I do like the code organization in `riscv-pac2` more. Mostly aesthetic preferences, but it does feel...