Rok Krajnc

I can't test this right now, so I'm just guessing, but it seems the problem might be operator precedence in this line: https://github.com/openrisc/mor1kx/blob/95eee0596a160ffdfd8ee6bc8b88268b2e49ec5e/rtl/verilog/mor1kx_execute_alu.v#L205 Besides, shouldn't the statement be using logical...

Hi, thanks for the report, I'll take a look and see if anything can be done.

https://github.com/sirdavid2 : I agree, but 100% compatibility will be hard to reach unless someone writes a cycle-accurate 68000/68020+ core.

Hi, thanks for pointing this out. In implemented design, there should be no issue. The synthesis tool should do 'the right thing', that is, ignore blocking assignment and treat it...

Yes, that looks correct. I would test if first though, just to be sure. While I wrote that the synthesis tool will do the right thing, you shouldn't assume that...

BTW, if you look at the code, you can see that if `copjmp1` was updated immediately, then the `if (copjmp1 && clk_ena)` would never be true, so this can't be...

Looking forward to your work on the vAmiga!

Hi, the CD32 gamepad support is not finished (I mentioned that in the release notes). It *should* work, if the docs I have are correct, but unfortunately it doesn't. Hopefully,...

Just to be sure, you are using a 'real' CD32 pad connected to the DB9 port, right? This should work *without* enabling the CD32Pad option in the OSD menu, that...

I didn't implement this correctly in the TG68 code - the C & CE bits should not be latched, it should be just a pulse that should signal the cache...